| section Home
Production, Amateur Radio amateur Model aircraft, rocket- Useful, entertaining |
Stealth master
Electronics Physics Technologies invention |
space Mystery
Earth Mysteries Secrets of the Ocean Stealth section Map |
  |
| Use of material is permitted for reference (for websites - hyperlinks) | |||
Navigation: => |
Home / Products Patents / In the section of the catalog / back / |
|
INVENTION
Russian Federation Patent RU2168827
EXTREME POWER REGULATOR SOLAR BATTERY
Name of the inventor: Gordeev K.G .; Obrusnik PV .; Polyakov SA .; Shpakovskaya GK
The name of the patentee: Federal State Unitary Enterprise Scientific-production center "Polyus"
Address for correspondence:
Starting date of the patent: 2000.02.08
The device can be used to control power energy converters in power systems (EPS) spacecraft with a solar battery (SB) as the primary source. Proposed extreme power regulator (ERM) performs search step Sa voltage at which it generates maximum power, and accordingly affects the power converters to maintain SEP Sa voltage at this point. To measure the SAT power is additionally introduced second down counter, the clock input of which receives pulses of a frequency proportional to the Security Council the current during the time interval proportional to the Security Council stress, and during one cycle occurs two dimensions SB power: before and after the displacement of the operating point of the Security Council CVC at second different directions down counter counting. To determine the Security Council the power change in the sign used by the output of the transfer counter. To generate the pulse frequency proportional to the current SAT, converter voltage is applied - the frequency and for periods of time of duration is proportional to the Security Council - the comparator and generator ramp. The device, while maintaining the digital method for processing information on SAT power is much simpler known analogues. There are no analog-to-digital converters, and digital comparator registers for storage and comparison of information SB power and communication line and multi-bit.
DESCRIPTION OF THE INVENTION
The invention relates to electrical engineering and can be used to control power energy converters in power systems (EPS) spacecraft with a solar battery (SB) as the primary source.
Security is characterized by a significant dependence of the power generated by voltage. Maximum efficiency of the SES spacecraft is achieved at a voltage on SAT close to optimal (U SBwholesale), in all modes of operation of BOT, in which it must generate maximum power. The natural condition of extreme power control Sa Sa is the separation of the busbars stable bus power onboard consumers and from the buffer storage bus - battery (AB) power conversion means. In the composition of EPA introduced additional devices, so-called extreme power regulators (ERM), serving to determine the operating point at which the energy generated by SB, maximum, and accordingly affecting the power converters BOT to maintain Sa voltage at this point. Inputs ERM supplied with voltage and current sensors SB voltage, and output voltage of the ERM corresponds to the voltage that must be maintained on the bus SB BOT power converting devices [1].
ERM uses a known mathematical method step extremum search. The algorithm of the ERM at this is as follows:
- Calculated and stored value of the power generated by the Security Council;
- ERM, affecting the power converting SES device changes (increasing or decreasing) the Security Council for a voltage value;
- Calculated value of the power generated by the Security Council at a voltage change;
- Comparing the stored and newly calculated values SB power.
If the resulting voltage change its SAT capacity increased, then the next cycle (step) operation ERM voltage change Sa made in the same direction, when, on the contrary, decreased - reversed.
Known ERM sat in analog-to-digital version, containing power Security sensor, built on the basis of two logarithmic and one antilogarifmicheskogo amplifier, capacitive storage device for storing the measured values SB power comparator for comparing the current and the stored values of the Security Council the power generator and the counter-valve, timing operation of the device, down counter and a digital to analog converter, outputs a device control signal to the power converting SEP devices [2].
This device has a low accuracy of the U SBwholesale because of the definition analog devices, storing and comparing the values of the Security Council the power.
The closest to the claimed is ERM, wherein the storage and comparison of SAT power information in digital form is produced (FIG. 1) [2].
FIG. 1 indicated:
1 - scaling amplifier;
2 - a first analog-to-digital converter;
3 - the first digital to analog converter;
4 - a second analog-to-digital converter;
5, 6 - registers;
7 - digital comparator;
8 - a clock generator;
9 - counter-distributor;
10 - an OR gate;
11 - logical AND gate;
12 - the trigger;
13 - down counter;
14 - a second digital to analog converter.
The device operates as follows.
Voltage proportional to Sa Sa current I is supplied to a scaling amplifier 1, and then converted into digital form the analog-digital converter (ADC) 2, and supplied to N inputs of the digital-analog converter (DAC) 3. The voltage U Sa Sa is input to voltage reference 3 DAC incorporated scheme multiplying DAC. Thus, the analog value of the voltage at the output of the DAC 3 in proportion to the current value of the power of the Security Council (P = I SATSATSAT · U).
At the output of the ADC 4 is formed by n-bit digital code corresponding to the value of the power consumed by Sa currently.
A clock generator 8 and counter 9 Distribution synchronized operation.
According to the clock pulse output from the 3-meter distributor said code 9 "stored" in the registers 5 and 6.
According to the clock pulse from the output of the counter 4-way valve 9 is changed Q1-Qm digital code output down counter 13 and accordingly, the output voltage of the second DAC 14, i.e. the output device.
When changing the voltage at the output of ERM power converters EPAs begin to stabilize other value SB voltage is slightly different from the previous one.
After changing the position of the operating point of the digital code corresponding to the new value of the power consumed by the Security Council at this time is recorded in the register 5 (on a signal output from the 7-meter distributor) and compares the digital comparator 7 with the last stored in the register 6. The appearance of the outlet A <B digital comparator 7 a logical "1" means a reduction in power as a result of step ST bias the operating point Council. In this case, the signal output from the 8-meter distributor 9 passes through the AND gate 11 to trigger input 12 and throws it, thereby changing the direction of count down counter 13.
If, for example, up to this time code and the digital output voltage is increased in ERM, the next pulse output from the four-way valve 9 of the counter result in their reduction. Accordingly, following the displacement of the working point of the Security Council the situation will occur in the other direction.
If as a result of displacement of the operating point was an increase in capacity of the Security Council (or if it remained unchanged), counting direction will not change, since the output A <B digital comparator is a logic "0", which prohibits the passage of the pulse output from the 8 tion counters distributor 9 via an AND gate 11. This happens search step Sa voltage at which it generates maximum power.
The disadvantage of this device is its complexity, due to the presence of two analog-digital and a digital to analog converter for measuring the SAT power and converting its values into digital code, two registers and a digital comparator performing storing, storage and comparison of digital codes, and more internal links in the device due to the need to operate a multi-bit digital values Sa capacity (to provide reasonable accuracy the number of digits n ADC 2 and 4 shall not be less than eight).
The invention solves the problem of simplifying the apparatus and reducing the number of internal links.
This object is achieved by the fact that the device instead of the analog to digital and digital to analog converters for measuring Sa power used additionally introduced second down counter, the clock input of which receives the pulses with a frequency proportional to Sa current, during the interval of time proportional to Sa voltage wherein during one cycle of measurement takes place Sa two power before and after shifting the operating point for different directions of the second down counter counting. To determine the Security Council the power change in the sign used by the output of the transfer counter.
Thus, from the device, except for the two analog-digital and a digital to analog converter, are excluded both registers for storing power information SB, the digital comparator, and a multi-bit link.
To generate the pulse frequency proportional to the current SAT, converter is used "voltage-frequency", and for periods of time lasting, SB proportional to the voltage - the comparator and generator ramp.
To control the second device down counter incorporated in the second AND gate and the RS-flip-flop for changing the direction of counting of the counter.
FIG. 2 shows the structural and functional diagram of the device on FIG. 3 - an example of its implementation, and FIG. 4 - time diagram of the device.
FIG. 2 is indicated by:
1 - scaling amplifier;
8 - a clock generator;
9 - counter-distributor;
10 - an OR gate;
11 - the first AND gate;
12 - the trigger;
13 - the first down counter;
14 - analog converter;
15 - Converter "frequency-voltage";
16 - second AND gate;
17 - the second up-down counter;
18 - sawtooth generator;
19 - comparator;
20 - RS-trigger.
The device operates as follows.
On the device inputs come SB voltage (U SB) and a voltage proportional to the Security Council current (I SC). Voltage proportional to Sa current is fed through a scaling amplifier 1 to the input of "the frequency of the voltage" inverter 15, whose output pulses are output frequency f = a 1 · I sat, where k 1 - coefficient of proportionality (curve f in Fig 4.) entering a first input of AND gate 16.
The generator 8 generates clock pulses of frequency f T (Fig. 4) applied to C-counter input distributor 9 and the sawtooth generator 18. The sawtooth voltage U n (FIG. 4) is applied to one input of a comparator 19, and the second is input voltage Sat.
The pulse duration at the output of the comparator (K diagram in Figure 4.) proportional to the voltage value Sa:
t U = a · U SB / f T · U n,
where k - coefficient of proportionality; U n - the amplitude of the sawtooth voltage.
Since T and f U p constant values,
t U = a 2 · U Sat,
where k 2 = k / f T · U n - the constant factor.
At the output transfer CO (CO diagram in FIG. 4) of the second down counter 17, a normal high level voltage, that is logical "1". It switches to a low level (logic "0"), if the count output was maximal in the addition mode (logic level "1" at the input of setting the count direction "± 1") or a minimum in the subtraction mode (logic "0" level at the input "± 1").
Each output of the counter 9 allocator logic high level "1" appears only on a clock period T corresponding number N, that is initially present at the output of one pulse, then the output 2 and so on. D.
The pulse output from the one (N = 1, T, curve V1 in Fig. 4) of the counter is fed to a distributor-S RS-trigger input and the zero input R of second counter 17. The down counter is reset and in the addition mode is set (logic level "1" setting the count at the input direction "± 1", the curve V2 in Fig. 4).
The pulse output from the three (N T = 3), the distributor of the counter 9 is supplied through the OR gate 10 to the third input of the second AND gate 16 (V3 diagram in Fig. 4), allowing the passage of pulses of frequency f for t U duration to the clock input C of the second down counter 17 (curve C in FIG. 4) as the output CO of the second transfer down counter and hence, the fourth input of the second aND gate and a logic level "1".
The number of pulses that pass to the input of the second down counter 17 and, respectively, the digital code sets as a result of the output of the counter, the value proportional to the power SB
n U = f · T U = 1 to Sa · I · 2 · in the U SB = 3 to the P · Security,
where k 3 = k 1 · k 2 - factor of proportionality,
SB P = U · I SatSat - current value of the power of the Security Council.
The pulse from the output 4 (N T = 4, V4 diagram in Fig. 4), the distributor of the counter 9, acting on the C clock input of the first down counter 13 changes the digital code Q1-Qm at its output and, therefore, the output voltage of the digital to analog converter 14, that is, the output device.
Power converting device EPAs begin to stabilize the value of the new SB voltage is slightly different from the previous one. The power level generated Sa changes.
The new steady state level of the current Security Council - I 'Sat; Set the level of the Security Council stress - U 'Council. The pulse frequency of the inverter output, "the frequency of the voltage of" 15 changes and becomes equal to f = 1 · I 'Security Council. The pulse duration at the output of the comparator 19 and changes and becomes equal to t 'U = a 2 · U' Council.
On impulse output 5 (N = 5 T) the RS-trigger 20-meter distributor 9 sets the second down counter 17 in the subtraction mode (logic level "0" to "± 1" input).
The pulse output from the 7 (N T = 7) distributor counter 9 through the OR gate 10 rises to the third input of the second AND gate 16, permitting the passage of pulses of frequency f 'for t duration' U to the clock input C of the second down counter 17 ( as the fourth input of the second aND gate, as the output CO of the second transfer down counter, a logic level "1").
The number of pulses passing to the clock input C of the counter 17, in proportion to the new, change the power SB:
n 'U = a 3 · P' Council.
For example, it has become smaller. Then the second down counter 17 in the subtraction mode reaches the minimum (zero) value and output logical level continue transferring CO has "1".
Consequently, the pulse from the output of 8 (N T = 8, diagram V5 in FIG. 4), the distributor of the counter 9 will pass through the first AND gate 11 to the input of flip-flop 12 toggles to it and change the direction of counting of the first down counter 13 by changing the voltage level on Fitting its counting direction input "± 1" (V6 diagram in FIG. 4).
Thus, by reducing the power generated by Sa, Sa following the change in momentum to the voltage output of the counter 4-way valve 9 is in the other direction. That is, if the Security Council before the voltage has been reduced, then the next time it will be increased.
Next cycle of repeated counter-distributor.
Pulse output 1 (N T = 1 ') resets the second down counter 17 and sets it in the addition mode.
During the pulse output from the three (N = 3, T ') takes place the second pulse count down counter 17:
n 'U = a 3 · P' Council.
Pulse output 4 (N T = 4 ') of the counter 9 distributor changes the digital code Q1-Qm at the output of the first down counter 13 and accordingly, the output voltage of the digital to analog converter 14, ie, the output device.
Power converting device EPAs begin to stabilize the value of the new SB voltage is slightly different from the previous one. The power level generated Sa changes.
Set the level of the current Security Council - I '' Security Council; new steady voltage level SB - U '' Security Council. The inverter output pulse frequency "is the frequency of the voltage" 15 changes and becomes equal to f '' = a 1 · I '' Security Council. The pulse duration at the output of the comparator 19 and changes and becomes equal to t '' = a 2 · U '' Sat.
On impulse output 5 (N = 5 T ') RS-trigger 20-meter distributor 9 sets the second down counter 17 in the subtraction mode (logic level "0" to "± 1" input).
The pulse output from the 7 (N T = 7 ') of the counter-distributor 9 through the OR gate 10 is supplied to the third input of the second AND gate 16, allowing pulses passing frequently that f' 'for the duration t' 'U to a clock input of the second reversing counter 17 (as the fourth input of the second aND gate, as the output CO transfer level logic "1").
The number of pulses that can pass on the counter input is proportional to the new value of the changed power SB:
n '' U = a 3 · P '' Sat.
Suppose it became more. Consequently, n '' U> n ' U. Then, when the subtraction process at the minimum (zero) value at the output CO of the second transfer down counter 17 will be a logic "0". This signal is entered in the fourth input of the second AND gate 16, the following will prohibit the passage of pulses from the output transducer "voltage-to-frequency" clock input 15 to down counter 17. The counter stops, at the output CO transferring remain logic "0" level. This level will not pass through the first AND gate 11 output pulse is 8 (N = 8, T ') of the counter-direction distributor 9. counting the first down counter 13 does not change.
Therefore, if as a result of displacement of the operating point on the current-voltage characteristic of the SC was an increase in the power generated by the Security Council, following the displacement of the operating point is in the same direction.
Thus, an extreme power control step performs search Sa voltage at which it generates maximum power. The proposed device, while maintaining a method of processing digital information Sa known power substantially simpler because it does not contain an analog-to-digital converters, and registers to store a digital comparator for comparing the output signals of the SB, and a multi-bit link.
INFORMATION SOURCES
1. RF Patent 2101831, H 02 J 7/35, publ. 01/10/98, BE N 1, 1998.
2. Options for the design of extreme power stepper controllers solar / Shinyakov YA, Gordeyev KG, Cherdantsev SP, PV Obrusnik .// Proceedings VNIIEM. Electromechanical devices spacecraft. M., 1997, v. 97, p. 83-92.
CLAIM
Extreme regulator solar battery power, comprising a scaling amplifier, whose input is the first measuring input device, a clock pulse generator, whose output is connected to the inlet distributor counter, a fourth output is connected to the clock input of the first down counter, third, and seventh outputs are connected to the input of logic OR gate, and the eighth output being coupled to the first input of the first aND gate whose output is connected via a trigger to the input of the first direction of setting the count down counter, which outputs through the digital to analog converter connected to the output device, characterized in that it additionally introduced converter stress- the frequency of the second up-down counter, generator sawtooth voltage, the comparator, RS-flip-flop, and a second NAND gate, the output of scaling amplifier through the converter voltage - frequency coupled to the first input of the second aND gate, a clock generator connected to the input shaper sawtooth, an input connected to one input of the comparator, the second input of which is the second measuring input device and an output connected to the second input of the second aND gate, the third input of which is connected to the output of the OR gate, and the fourth is connected to the second input of the first aND gate and the output transfer of the second down counter, the clock input of which is connected to the output of the second aND gate, and the zero-setting input connected to the first output distributor counter is connected and the S-input of RS-flip-flop, the input R is connected to the fifth output distributor counter, and an output connected to the set input of the counter direction of the second down counter.
print version
Publication date 12.01.2007gg
Comments
Commenting, keep in mind that the content and the tone of your messages can hurt the feelings of real people, show respect and tolerance to his interlocutors, even if you do not share their opinion, your behavior in terms of freedom of speech and anonymity offered by the Internet, is changing not only virtual, but real world. All comments are hidden from the index, spam control.