Development of LVDS signal transmission technology
The amount of data transmitted - gigabits, consumption - milliwatts
The Low Voltage Differential Signaling Standard (LVDS) is today the best solution for systems with high-speed, low-power interfaces. When using LVDS, a high exchange rate is achieved with low energy consumption. Additional benefits include compatibility with low voltage power supplies, low noise and reliable signal transmission. For these reasons, this standard is widespread in production, in different market segments where speed and low consumption are needed. Typical examples of the application of this standard are the connection of boards and cables in switching switches, routers, industrial cameras, as well as in automotive entertainment information systems and car control systems. Even with all these advantages, there are some restrictions on the use in devices that require the support of multiple transceivers on one bus, power from the low voltage bus, and receivers with an extended common-mode signal range. This has led to the emergence of new LVDS standards that complement the original standard.
Low Voltage Differential Signaling Standard (LVDS)
In 1994, National Semiconductor first introduced LVDS as a standard interface. Bandwidth requirements were growing exponentially, and system developers were looking for ways to reduce power losses. Conventional standards, such as RS-422 and RS-485, lacked speed, while ECL (logic circuits with emitter connections) and CML (logic circuits with current switches) had a sufficient exchange rate, but consumed too much power. LVDS technology helped solve this problem without any compromise. This is a differential technology, that is, it uses two lines to transmit a signal (Fig. 1). In addition, when using LVDS, a signal with a current loop is transmitted, and the logical level (high or low) is determined by the direction of the current in the loop (clockwise or counterclockwise). About 3.5 mA goes through one wire of the pair and returns in another. A voltage is created at the termination resistor (about ± 3.5 mA x 100 Ohms = ± 350 mV). The receiver, a differential comparator, determines the polarity of the voltage drop, while a positive voltage value corresponds to a high level of logic, a negative value to a low one. The driver provides 350 mV of differential output voltage with a center of approximately +1.25 V. The receiver threshold is set to 100 mV with an input range of 0 to +2.4 V. This allows the rated active signal to shift down or up by 1 V common mode due to the potential difference of the earth. The driver is intended for use with a load of 100 ohms, with a terminating resistor of 100 ohms.
Figure 1. A simplified diagram of the LVDS driver and driver connected through a carrier with a differential impedance of 100 Ohms
The differential concept results in a high gain in the form of common mode rejection. Due to its high noise immunity, the signal amplitude can be reduced to just a few hundred millivolts. A smaller amplitude allows for faster data exchange, since the rise and fall of the signal are well controlled and kept within 1 V / ns. A relatively constant small output current reduces background noise and power noise. Since the current in the transmitting pair is a closely connected current loop, the electric scattering fields often disappear, reducing electromagnetic interference. The exchange rate is different depending on each individual device, but in any case it is within 1.5 Gbit / s at constant current. Power is minimized in three ways. The load current is limited to 3.5 mA, the current driver usually limits dynamic power dissipation, and the quiescent current is minimized by CMOS processes at the submicron level. Low Voltage Differential Signaling (LVDS) is defined in the ANSI / TIA / EIA-644-A-2001 standard, which is an update to the 1995 ANSI / TIA / EIA-644 standard. This standard defines only the LVDS electrical signal levels, i.e. the characteristics of the driver output and receiver input. This standard must be applied in conjunction with other standards defining a complete interface, including protocol, connections, and media. These are standards such as Camera Link or the interface FPD standard for laptops, defined by the SPWG (Working Group of Standard Consoles), and it is also used in many special applications. In addition, there are other standards. In fig. Figure 2 shows the signal amplitudes and bias voltages (respectively) of various LVDS standards.
Figure 2. Oscillations of differential signals and bias comparison
To date, LVDS crystals and crystal sets with many functions are offered by several companies. In addition to simple linear drivers and receivers that convert between the LVDS and LVTTL levels, there are LVDS – LVDS buffers, coordinate switches, signal distributors (splitters), and clock distribution devices.
Of particular interest are sets of crystals for conversion from parallel to serial form and vice versa (SerDes), since they increase the speed of LVDS, which gives a great advantage to the whole system. LVDS technology provides the ability to integrate I / O with additional circuits such as: PLL circuit (phase-locked loop) for conversion from parallel to serial form; with a latch register and even with digital circuits, for example with a test port of a peripheral automatic network with switched channels (Boundary SCAN Test Access Port). In fig. Figure 3 shows an example of a similar set of SerDes crystals. The SCAN92LV1025 parallel-to-serial converter collects 10 slow input signals from TTL circuits and converts them into serial form on one high-speed LVDS channel.
Figure 3. Crystal LVDS parallel-to-serial converter / serial-to-parallel converter with added JTAG test
The transmitter clocks are embedded in the serial data stream by marking the data with start (HIGH) and stop (LOW) bits. The narrow LVDS interface does not require the use of multiple contacts, bulky heavy connectors and cables, which in turn reduces the cost of the system. The SCAN92LV1226 serial to parallel converter receives the LVDS signal, extracts the synchronization signal from the data stream, and creates a 10-bit TTL bus. The throughput of this chip can reach 800 Mbps of useful information. Similar technical solutions of SerDes are ideal for those systems where it is necessary to use thin wiring, for example, video sensor connections in car chassis, manipulators, connections to measuring heads in automatic verification equipment, etc. There are some limitations to LVDS, such as an in-phase signal ± 1 V and a final load of 100 ohms. This caused several variations of the LVDS 1 standard.
1) For example:
- ANSI / TIA / EIA-644 LVDS standard.
- ANSI / TIA / EIA-644-A LVDS standard.
- ANSI / TIA / EIA-899 M-LVDS standard.
- JEDEC GLVDS Specification, Version 1.0.
- JEDEC SLVS (JESD8-13) October 2001.
LVDS is primarily used in special high-speed point-to-point connections. The driver needs coordination with the line, and the connection parameters should be selected based on the characteristic input resistance of the cable. Thanks to this, a high quality signal transmission is achieved, and its reflection and radiation are minimized. To explain the difference between the options for implementing LVDS technology, it is necessary to recall the basic bus configurations, the various designs of which are shown in Fig. 4. The simplest is a unidirectional bus with two points, at the end of the cable there is only one terminating resistor, and the driver is always located on the opposite end of the cable. Due to its high noise immunity, the point-to-point configuration supports high data rates. This bus structure makes it easy to create gigabit networks. At the same time, for bi-directional data transmission, it is necessary to allocate a separate line (2 pairs). In this case, temporary data transmission in two directions can be carried out, and the throughput of the common bus is doubled.
Figure 4. Various bus topologies
Another common configuration is a classic distribution system or multi-drop bus. Using this configuration is especially effective if you need to transfer the same information to several points at once. As in the previous case, the driver is located at one end of the bus, and the terminating resistor is at the other. Along the bus are two or more receivers with small connecting wires. The electrical length of these wires should be as small as possible to prevent a decrease in signal quality due to the effect of reflection, interference, etc. The exchange rate when using multi-point buses can reach 400–600 Mbit / s depending on the connecting wires and the load. The most flexible configuration is a multi-point bus with matching at both ends of the connecting wire. The driver can be located anywhere on the bus. The operation of several drivers at the same time is not possible, therefore data transmission is two-sided half duplex. Connecting network nodes to the bus can be critical, so it should be done carefully. For systems with two terminating resistors, the so-called multipoint systems, more powerful drivers are needed to create oscillations similar to LVDS, while the load ranges from 30 to 50 ohms.
Derivatives of LVDS
The table shows the main parameters of some varieties of LVDS.
Table 1. Comparison table of LVDS
|Output amplitude||250 - 450 mV||240 - 500 mV||480 - 650 mV||150 - 500 mV||247 - 454 mV|
|Bias voltage||1.125 V||1.3 V||0.3 - 2.1 V||75 - 250 mV||1.125 V|
|Completion||100 W||27 - 50 W||50 W||Internal to RX||50 W|
|Field current||2.5 - 4.5 mA||9 - 17 mA||9 - 13 mA||Adjustable||6 mA|
|Short circuit current||<24 mA||<65 mA||<43 mA||-||10 mA|
|Thresholds||± 100 mV||± 100 mV||± 50 mV||± 100 mV||± 100 mV|
|Input voltage||0 to +2.4 V||0 to +2.4 V||-1.4 to +3.8 V||-0.5 to +1 V||0 to +2.4 V|
|Common mode||± 1 V||± 1 V||± 2 V||± 0.5 V||± 1 V|
In 1997, National Semiconductor introduced the LVDS bus for controlling high-load, low-impedance circuit boards. Boards with a large number of cards (up to 20 pieces) in a small space usually have an input impedance of 50-60 ohms. When matching at both ends in a size of, for example, 54 ohms, the driver actually encounters a load of 27 ohms. To obtain LVDS amplitudes, the driver output current must be tripled to a range of 10–12 mA. Another improvement of this technology was the coordination of the total output impedances of the driver, as well as the technology of preventing the simultaneous use of one channel. If several drivers try to access the bus simultaneously, the output current will be lowered so as not to damage the I / O devices.
A newer version of LVDS is the ANSI / TIA / EIA-899 standard, known as M-LVDS (Multipoint-LVDS - Multipoint LVDS). This version supports a multi-point bus with double matching and can use up to 32 nodes. M-LVDS also extends the common mode range to ± 2 V. The maximum data transfer rate is 500 Mbps. In practice, the speed is limited to 300-400 Mbit / s depending on various parameters, such as the length of the connecting wire and the required signal quality. M-LVDS has an output current of 9–13 mA and refers to both the cable and the board connections. When using long cables, the likelihood of a large difference between the potentials of the earth increases. Thus, the M-LVDS standard doubled the range of the common mode LVDS to ± 2 V for greater stability. M-LVDS also distinguishes between two types of receivers (Fig. 5). Type 1, called the “data receiver,” has thresholds of ± 50 mV with a typical hysteresis of 30 mV. Type 2 or “control receiver” switches the output to LOW when the input voltage drops below 50 mV. The output switches to HIGH when the input voltage is above 150 mV. The advantage of shifting the threshold region by +50 mV is the appearance of a 50 mV noise immunity margin.
Figure 5. M-LVDS Type 1 and Type 2 Receiver
The outputs in this case are switched to the LOW position (trouble-free operation). By the way, M-LVDS was chosen by PICMG (PCI group for the production of computers for industry) as a signal transmission standard for distributing clock signals in ATCA-compatible data transmission systems (ATCA - a modern architecture of computers for telecommunications).
GLVDS (related to land LVDS) - development of one of the largest telecommunications companies. GLDVS technology is similar to LVDS, except that the offset of the driver output voltage is closer to the ground potential. By lowering the bias voltage, the GLVDS inputs and outputs can be integrated into specialized ICs and run on low voltage sources of 0.5 V. GLVDS is currently being considered by the JEDEC Standardization Committee for adoption as a standard. JEDEC has already published one standard that has much in common with GLVDS. This is the SLVS standard, which stands for “Variable Low Voltage Transmission for 400 mV” (JESD8-13). This interface is consistent with ground potential and has two options for drivers and receivers. Receivers can be either one-way or differential, and drivers can be for both point-to-point and multipoint applications. The exchange rate varies in the range of 1-3 Gbit / s, but only over short distances (less than 30 cm). Therefore, the application of this interface is limited to the region of high-speed connections from crystal to crystal. Due to an amplitude of 400 mV and ground matching, the voltage of the power bus is only 0.8 V. Thus, this interface is compatible with the low voltage cores used in ultra-thin crystals of specialized ICs.
Texas Instruments has developed a series of components designed for 100 Ohm double matching applications. The driver output current is twice as high as the standard for LVDS, i.e. 6 mA nominally. Thus, at a load of 50 ohms, LVDS levels are achieved. This technology can be used when working with bidirectional point-to-point buses or multi-drop tires with a small load.
The LVDS standard provides the developer with the opportunity not to sacrifice the necessary characteristics of the system. Using this standard, data is transmitted at high speed, it consumes little electricity, the system is immune to noise and there is little electromagnetic interference. New types of LVDS best complement the original standard and allow it to be used in even more applications. In the near future, data transfer rates will increase, and the supply voltage will drop. In conditions of lowering energy consumption, decreasing electromagnetic and crosstalk, the tendency towards a decrease in amplitudes, which began with the creation of LVDS, is likely to continue in subsequent years.
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