This page has been robot translated, sorry for typos if any. Original content here.

The development of signal transmission technology LVDS

The volume of transmitted data - gigabits, consumption - milliwatts


The Low Voltage Differential Signal Transmission Standard (LVDS) is today the best solution for systems with high-speed, low-power interfaces. When using LVDS, a high exchange rate is achieved with low energy consumption. Additional benefits include compatibility with low voltage power supplies, low noise and reliable signal transfer. For these reasons, this standard is widely used in manufacturing, in different market segments where speed and low consumption are necessary. Typical examples of the application of this standard are the connections of boards and cables in switching switches, routers, industrial cameras, as well as in automotive infotainment systems and car control systems. Even with all these advantages, there are some restrictions on the use of devices requiring the support of multiple transceivers on a single bus, power from a low-voltage bus, and receivers with an extended common-mode signal range. This has led to the emergence of new LVDS standards, complementing the original standard.

Low Voltage Differential Signal Transmission Standard (LVDS)

In 1994, National Semiconductor for the first time introduced low-voltage differential signaling (LVDS) technology as a standard interface. Bandwidth requirements grew exponentially, and system developers looked for ways to reduce power loss. Normal standards, such as RS-422 and RS-485, lacked speed, while ECL (emitter-coupled logic circuits) and CML (current-switching logic circuits) had a sufficient exchange rate, but consumed too much electricity. LVDS technology helped solve this problem without any compromises. This is a differential technology, that is, it uses two lines to transmit a signal (Fig. 1). In addition, when using LVDS, a signal is transmitted from the current loop, and the logical level (high or low) is determined by the direction of the current in the loop (clockwise or counterclockwise). Approximately 3.5 mA goes through one pair of wire and returns via the other. A voltage is generated on the terminating resistor (about ± 3.5 mA x 100 Ω = ± 350 mV). The receiver, a differential comparator, determines the polarity of the voltage drop, with a positive voltage value corresponding to a high logic level, a negative value - to a low one. The driver provides 350 mV differential output voltage with a center of approximately +1.25 V. The receiver threshold is set to 100 mV with an input range from 0 to +2.4 V. This allows the nominal active signal to move down or up to 1 V common mode due to potential difference of the earth. The driver is designed for use with a load of 100 ohms, with a 100 ohm terminating resistor.

Simplified diagram of the driver and receiver LVDS, connected through a carrier with a differential impedance of 100 Ohms
Figure 1. Simplified diagram of the driver and receiver LVDS, connected through a carrier with a differential impedance of 100 Ohms

The differential concept results in high gain in the form of common mode rejection. Due to its high resistance to noise, the signal amplitude can be reduced to just a few hundred millivolts. Smaller amplitude allows data exchange faster, since the rise and fall of the signal is well controlled and held within 1 V / ns. A relatively constant small output current reduces background noise and power noise. Since the current in the transmitting pair is a closely related current loop, the stray electric fields often disappear, reducing electromagnetic interference. The exchange rate is different depending on each individual device, but in any case it is within 1.5 Gbit / s at a constant current. Power is minimized in three ways. The load current is limited to 3.5 mA, the current mode driver usually limits dynamic power dissipation, and the quiescent current is reduced to a minimum using CMOS processes at the submicron level. Low-voltage differential signaling (LVDS) is defined in the ANSI / TIA / EIA-644-A-2001 standard, which is an update to the 1995 ANSI / TIA / EIA-644 standard. This standard specifies only the levels of LVDS electrical signals, that is, the characteristics of the driver output and receiver input. This standard should be used in conjunction with other standards that define the complete interface, including protocol, connections, and media. These are standards such as the Camera Link or FPD interface standard for laptops, defined by the SPWG (Working Group of Standard Consoles), it is also used in many special applications. In addition, there are other standards. In fig. 2 shows the amplitudes of the signals and the bias voltage (respectively) of various LVDS standards.

Differential signal oscillations and displacement comparison
Figure 2. Differential signal oscillations and displacement comparison

To date, LVDS crystals and crystal sets with many features are offered by several companies. In addition to simple linear drivers and receivers that perform conversion between LVDS and LVTTL levels, there are LVDS – LVDS buffers, coordinate switches, signal distributors (splitters), and clock distribution devices.

Of particular interest are sets of crystals for conversion from parallel to serial form and vice versa (SerDes), since they increase the speed of LVDS, which gives a great advantage to the system as a whole. The LVDS technology provides for the possibility of integrating I / O with additional circuits such as: a PLL (Phase Automatic Frequency Tuning) circuit for converting from parallel to serial form; with a register latch and even with digital circuits, for example with a test port of a peripheral automatic network with switched channels (Boundary SCAN Test Access Port). In fig. 3 shows an example of such a set of SerDes crystals. A parallel to serial converter SCAN92LV1025 collects 10 slow input signals from TTL circuits and converts them into serial form over one high-speed LVDS channel.

Parallel to Serial LVDS Converter / Serial to Parallel Transducer with JTAG Test Added
Figure 3. LVDS crystal from parallel to serial / converter from serial to parallel with JTAG test added

Transmitter clock signals are embedded in the serial data stream by marking data with start (HIGH) and stop (LOW) bits. The narrow LVDS interface does not require the use of multiple pins, bulky heavy connectors and cables, which, in turn, reduces the cost of the system. The converter from serial to parallel SCAN92LV1226 receives the LVDS signal, extracts the synchronization signal from the data stream and creates a 10-bit TTL bus. The capacity of this crystal can reach 800 Mbps of useful information. Such technical solutions SerDes are ideal for those systems where it is necessary to use thin wiring, for example, connections of video sensors in automobile chassis, manipulators, connections with measuring heads in automatic testing equipment, etc. There are some limitations of the LVDS, for example, a common-mode signal level of ± 1 V and a final load of 100 Ω. This caused several variations of the LVDS 1 standard.

1) For example:

  1. ANSI / TIA / EIA-644 LVDS standard.
  2. ANSI / TIA / EIA-644-A LVDS standard.
  3. ANSI / TIA / EIA-899 M-LVDS standard.
  4. JEDEC GLVDS specification, version 1.0.
  5. JEDEC SLVS (JESD8-13) October 2001.

Bus topology

LVDS is primarily used in special high-speed point-to-point connections. The driver needs matching with the line, and the connection parameters should be selected based on the characteristic input resistance of the cable. Due to this, a high quality of signal transmission is achieved, and its reflection and radiation are minimized. To explain the difference between the LVDS technology implementation options, it is necessary to recall the basic tire configurations, the various designs of which are shown in fig. 4. The simplest is a two-point unidirectional bus, which has only one terminating resistor at the end of the cable, and the driver is always at the opposite end of the cable. Due to its high noise immunity, the “point-to-point” configuration supports high data exchange rates. This bus structure makes it easy to create gigabit networks. At the same time for bidirectional data transfer it is necessary to allocate a separate line (2 pairs). In this case, a temporary transfer of data in two directions can be carried out, and the capacity of the common bus is doubled.

Different bus topologies
Figure 4. Different bus topologies

Another common configuration is the classic distribution system or multipoint bus. Using this configuration is especially effective if you need to transfer the same information to several points at once. As in the previous case, the driver is located at one end of the bus, and the terminating resistor is at the other. Along the bus are two or more receivers with small connecting wires. The electrical length of these wires should be as short as possible to prevent a reduction in signal quality due to the effect of reflection, interference, etc. The exchange rate when using multipoint busses can reach 400–600 Mbit / s depending on the connecting wires and the load. The most flexible configuration is a multipoint bus with matching on both ends of the connecting wire. The driver can be anywhere on the bus. The operation of several drivers at the same time is impossible, therefore data transmission is two-sided half-duplex. Connecting network nodes to the bus can be critical, so it should be done carefully. For systems with two matching resistors, the so-called multipoint systems, more powerful drivers are needed to create oscillations like LVDS, while the load ranges from 30 to 50 Ohms.

LVDS derivatives

The table shows the main parameters of some varieties of LVDS.

Table 1. Comparative table LVDS

Parameter Lvds Blvds M-LVDS GLVDS LVDM
Output amplitude 250 - 450 mV 240 - 500 mV 480 - 650 mV 150 - 500 mV 247 - 454 mV
Offset voltage 1.125 V 1.3 V 0.3 - 2.1 V 75 - 250 mV 1.125 V
Completion 100 W 27 - 50 W 50 W Internal to RX 50 W
Excitation current 2.5 - 4.5 mA 9 - 17 mA 9 - 13 mA Regulated 6 mA
Short circuit current <24 mA <65 mA <43 mA - -10 mA
Rapids ± 100 mV ± 100 mV ± 50 mV ± 100 mV ± 100 mV
Input voltage 0 to + 2.4V 0 to + 2.4V -1.4 to +3.8 V -0.5 to +1 V 0 to + 2.4V
Common mode ± 1 V ± 1 V ± 2 V ± 0.5 V ± 1 V

LVDS tire

In 1997, National Semiconductor introduced the LVDS bus for controlling high-load boards with low input impedance. Boards with a large number of cards (up to 20 pieces) in a small space usually have an input resistance in the range of 50–60 Ohm. When negotiating at both ends in the size of, for example, 54 Ohms, the driver actually faces a load of 27 Ohms. To obtain LVDS amplitudes, the driver output current must be tripled to a range of 10–12 mA. Another improvement of this technology was the coordination of the full output impedances of the driver, as well as the technology to prevent the simultaneous use of one channel. If several drivers are trying to access the bus simultaneously, the output current will be lowered so as not to damage the I / O devices.


A newer version of LVDS is the ANSI / TIA / EIA-899 standard, known as M-LVDS (Multipoint-LVDS - multipoint LVDS). This version supports multi-point bus with double matching and can use up to 32 nodes. M-LVDS also extends the common mode range to ± 2 V. The maximum data transfer rate is 500 Mbps. In practice, the speed is limited to 300-400 Mbit / s depending on various parameters, such as the length of the connecting wire and the required signal quality. M-LVDS has an output current of 9–13 mA and addresses both the cable and the board connections. When using long cables, the likelihood of a large difference between the potentials of the earth increases. Thus, the M-LVDS standard doubled the range of the common mode LVDS to ± 2 V for greater stability. M-LVDS also distinguishes between two types of receivers (Figure 5). Type 1, called the “data receiver”, has thresholds of ± 50 mV with a typical hysteresis of 30 mV. Type 2 or “control receiver” switches the output to the LOW position when the input voltage drops below 50 mV. The output switches to the HIGH position when the input voltage is above 150 mV. The advantage of shifting the threshold region by +50 mV is the appearance of a 50 mV noise margin.

Receiver M-LVDS type 1 and type 2
Figure 5. M-LVDS type 1 and type 2 receiver

Outputs in this case are switched to the LOW position (trouble-free mode). By the way, M-LVDS was chosen by PICMG (PCI group for the production of computers for industry) as a signaling standard for the distribution of clock signals in ATCA-compatible data transmission systems (ATCA is a modern computer architecture for telecommunications).


GLVDS (correlated with the land LVDS) - the development of one of the largest telecommunications companies. GLDVS technology is similar to LVDS, except that the driver output voltage offset is closer to the ground potential. By reducing the voltage offset, the GLVDS inputs / outputs can be integrated into specialized ICs and operate from low voltage sources of 0.5 V. The GLVDS is currently being considered by the JEDEC Standardization Committee for adoption as a standard. JEDEC has already published one standard that has a lot in common with GLVDS. This is a standard SLVS, which stands for “variable transmission of low voltage signals for 400 mV” (JESD8-13). This interface is consistent with ground potential and has two options for drivers and receivers. Receivers can be both one-way and differential, and drivers can be used for both point-to-point and multipoint applications. The exchange rate varies in the range of 1-3 Gbit / s, but only over short distances (less than 30 cm). Therefore, the use of this interface is limited to the area of ​​high-speed connections from crystal to crystal. Due to the amplitude of 400 mV and ground matching, the supply bus voltage is only 0.8 V. Thus, this interface is compatible with low-voltage cores used in ultra-thin crystals of specialized ICs.


Texas Instruments has developed a series of components designed for dual-matching 100-ohm applications. The driver output current is twice the standard for LVDS, that is, 6 mA nominally. Thus, at a load of 50 ohms, LVDS levels are achieved. This technology can be used when working with bidirectional point-to-point tires or multipoint tires with a small load.


The LVDS standard provides the developer with an opportunity not to sacrifice the necessary characteristics of the system. When using this standard, data is transmitted at high speed, little energy is consumed, the system is resistant to noise and little electromagnetic interference is generated. New types of LVDS best complement the original standard and allow it to be used in an even greater number of application systems. In the near future, data rates will increase, and the supply voltage will drop. In the conditions of lower power consumption, reduction of electromagnetic and crosstalk, the tendency for amplitudes to decrease, which was initiated by the creation of LVDS, is likely to continue in subsequent years.

You can purchase products and order free samples of National Semiconductor from official dealers - KOMPEL and Rainbow Technologies.